Use aligned prefetch address

Prefetch always form a chache line boundary. It seems
that if prefetch address is not cache line aligned then
performance is adversely impacted.

Hopefully we will resuse that 32 bits of padding for something
useful in the future.

Signed-off-by: Marco Costalba <mcostalba@gmail.com>

diff --git a/src/tt.cpp b/src/tt.cpp
index 862842f..770e38b 100644 (file)
--- a/src/tt.cpp
+++ b/src/tt.cpp
@@ -34,7 +34,7 @@
 #endif
 
 // This is the number of TTEntry slots for each position
-static const int ClusterSize = 5;
+static const int ClusterSize = 4;
 
 // The main transposition table
 TranspositionTable TT;

diff --git a/src/tt.h b/src/tt.h
index 0b7ccbe..e838b09 100644 (file)
--- a/src/tt.h
+++ b/src/tt.h
@@ -70,6 +70,7 @@ private:
   uint32_t data;
   int16_t value_;
   int16_t depth_;
+  uint32_t pad_to_16_bytes;
 };
 
 /// The transposition table class.  This is basically just a huge array